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a ad7650 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 16-bit, 570 ksps low cost cmos adc functional block diagram switched cap dac 16 control logic and calibration circuitry clock ad7650 data[15:0] busy rd cs ser/par ob/2c ognd ovdd dgnd dvdd avdd agnd ref refgnd in+ in pd reset serial port parallel interface cnvst warp impulse features throughput 570 ksps (warp mode) 500 ksps (normal mode) 16 bits resolution analog input voltage range: 0 v to 2.5 v no pipeline delay parallel and serial 5 v/3 v interface spi ?/ qspi ?/ microwire ?/ dsp compatible single 5 v supply operation power dissipation 77 mw typical @ 444 ksps (impulse mode) 21 w @ 100 sps power-down mode: 7 w max package: 48-lead quad flat pack (lqfp) or 48-lead frame chip-scale pack (lfcsp) pin-to-pin compatible with pulsar adcs applications data acquisition instrumentation digital signal processing spectrum analysis medical instruments battery-powered systems process control general description the ad7650 is a 16-bit, 570 ksps, charge redistribution sar, analog-to-digital converter that operates from a single 5 v power supply. the part contains a high-speed 16-bit sampling adc, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. it features a very high sampling rate mode (warp) and, for asynchronous conversion rate applications, a fast mode (normal) and, for low power applications, a reduced power mode (impulse) where the power is scaled with the throughput. it is fabricated using analog devices high-performance, 0.6 micron cmos process and is available in a 48-lead lqfp or in a tiny 48-lead chip scale package with operation specified from C40 c to +85 c. product highlights 1. fast throughput the ad7650 is a 570 ksps, charge redistribution, 16-bit sar adc. 2. single-supply operation the ad7650 operates from a single 5 v supply. in im pulse mode, its power dissipation decreases with the throughput from 77 mw at 444 ksps throughput to, for in stance, only 21 w at a 100 sps throughput. it consumes 7 w maximum when in power-down. 3. serial or parallel interface versatile parallel or 2-wire serial interface arrangement com- patible with both 3 v or 5 v logic. spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corporation.
ad7650especifications (e40 c to +85 c, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted.) #$# parameter condition min typ max unit resolution 16 bits analog input voltage range v in+ e v ine 0v ref v operating input voltage v in+ e0.1 +3 v v ine e0.1 +0.5 v analog input cmrr f in = 10 khz 62 db input current 570 ksps throughput 7 a input impedance see analog input section throughput speed complete cycle in warp mode 1.75 s throughput rate in warp mode 1 570 ksps time between conversions in warp mode 1 ms complete cycle in normal mode 2 s throughput rate in normal mode 0 500 ksps complete cycle in impulse mode 2.25 s throughput rate in impulse mode 0 444 ksps dc accuracy integral linearity error e6 +6 lsb 1 no missing codes 15 bits transition noise 0.7 lsb full-scale error 2 ref = 2.5 v 0.12 % of fsr unipolar zero error 2 5 25 lsb 3 power supply sensitivity avdd = 5 v 5% 3 lsb ac accuracy signal-to-noise f in = 100 khz 86 db 4 spurious free dynamic range f in = 100 khz 98 db total harmonic distortion f in = 45 khz e98 db f in = 100 khz e96 db signal-to-(noise + distortion) f in = 100 khz 86 db e60 db input, f in = 100 khz 30 db e3 db input bandwidth 18 mhz sampling dynamics aperture delay 2 ns aperture jitter 5 ps rms transient response full-scale step 250 ns reference external reference voltage range 2.3 2.5 avdd e 1.85 v external reference current drain 570 ksps throughput 115 a digital inputs logic levels v il e0.3 +0.8 v v ih 2.0 ovdd + 0.3 v i il e1 +1 a i ih e1 +1 a digital outputs data format parallel or serial 16-bit pipeline delay conversion results available immediately after completed conversion v ol i sink = 1.6 ma 0.4 v v oh i source = e500 a ovdd e 0.6 v power supplies specified performance avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.7 5.25 v
#%# ad7650 timing specifications parameter symbol min typ max unit refer to figures 8 and 9 convert pulsewidth t 1 5ns time between conversions t 2 1.75/2/2.25 note 1 s (warp mode/normal mode/impulse mode) cnvst n n cnvst n cs cs cs cnvst n n n c n ( e 40 c to +85 c, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted.) #%# ad7650
ad7650 #&# timing specifications parameter symbol min typ max unit refer to figures 13 and 14 (continued) sclk last edge to sync delay t 24 3 cs cs cs n cnvst n (continued) i oh 500 a 1.6ma i ol to output pin 1.4v c l 60pf in serial interface modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10pf; otherwise, the load is 60pf maximum. '
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#2# ad7650 ordering guide model temperature range package description package option ad7650ast e40 c to +85 c quad flatpack (lqfp) st-48 ad7650astrl e40 c to +85 c quad flatpack (lqfp) st-48 ad7650acp 1 e40 c to +85 c quad flatpack (lfcsp) cp-48 1 ad7650acprl 1 e40 c to +85 c quad flatpack (lfcsp) cp-48 1 eval-ad7650cb 2 evaluation board eval-control brd2 3 controller board notes 1 future product. contact factory for availability. 2 this board can be used as a standalone evaluation board or in conjunction with the eval-control brd2 for evaluation/demonstrati on purposes. 3 this board allows a pc to control and communicate with all analog devices evaluation boards ending in the cb designator. absolute maximum ratings 1 analog inputs in+ 2 , ref, ine, refgnd . . . . . . . . . . . . avdd + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to agnd e 0.3 v ground voltage differences agnd, dgnd, ognd . . . . . . . . . . . . . . . . . . . . 0.3 v supply voltages avdd, dvdd, ovdd . . . . . . . . . . . . . . . . . . . . . . . 7 v avdd to dvdd, avdd to ovdd . . . . . . . . . . . . . 7 v dvdd to ovdd . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v digital inputs except the data bus d(7:4) . . . . e0.3 v to dvdd + 0.3 v data bus inputs d(7:4) . . . . . . . e0.3 v to ovdd + 0.3 v internal power dissipation 3 . . . . . . . . . . . . . . . . . . . 700 mw junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150 c storage temperature range . . . . . . . . . . . e65 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 see analog input section. 3 specification is for device in free air: 48-lead lqfp: ja = 91 c/w, jc = 30 c/w. 48-lead lfcsp: jc = 26 c/w. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7650 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
ad7650 #3# pin function descriptions pin no. mnemonic type description 1 agnd p analog power ground pin 2 avdd p input analog power pins. nominally 5 v. 3, 40e42, nc no connect 44e48 4 dgnd di must be tied to the ground where dvdd is referred. 5 ob/2c di straight binary/binary two?s complement. when ob/2c is high, the digital output is straight binary; when low, the msb is inverted resulting in a two?s complement output from its internal shift register. 6 warp di mode selection. when high and impulse low, this input selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. when low, full accuracy is maintained independent of the minimum conversion rate. 7 impulse di mode selection. when high and warp low, this input selects a reduced power mode. in this mode, the power dissipation is approximately proportional to the sampling rate. 8 ser/ par par par int par int int par par par par 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) agnd
pd reset dgnd agnd av d d nc dgnd ob/ warp impulse nc = no connect ser/ d0 d1 d2 busy d15 d14 d13 ad7650 d3 d12 d4/ext/
d5/invsync d6/invsclk d7/rdc/sdin ognd ovdd dvdd dgnd d8/sdout d9/sclk d10/sync d11/rderror nc nc nc nc nc in+ nc nc nc in e refgnd ref
#4# ad7650 pin function descriptions (continued) pin no. mnemonic type description 16 data[7] di/o when ser/ par par int int int par par int int par par int par par int par par int par rd cs rd cs cs rd cs
ad7650 #5# definition of specifications integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. full-scale error the last transition (from 011 . . . 10 to 011 . . . 11 in two?s comple- ment coding) should occur for an analog voltage 1 1/2 lsb below the nominal full scale (2.49994278 v for the 0 ve2.5 v range). the full-scale error is the deviation of the actual level of the last transition from the ideal level. unipolar zero error the first transition should occur at a level 1/2 lsb above analog ground (19.073 v for the 0 ve2.5 v range). unipolar zero error is the deviation of the actual transition from that point. spurious free dynamic range (sfdr) the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to s/(n+d) by the following formula: enob s n d db
176 602 ./. and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic compo- nents to the rms value of a full-scale input signal and is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal to (noise + distortion) ratio (s/[n+d]) s/(n+d) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/(n+d) is expressed in decibels. aperture delay aperture delay is a measure of the acquisition performance and is measured from the falling edge of the cnvst cnvst cnvst cnvst
#6# ad7650 typical performance characteristics e code inl e lsb 4 3 e 4 0 16384 65536 32768 49152 0 e 1 e 2 e 3 2 1 +7*(
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* code e hexa counts 8001 7ffc 8000 7ffd 7fff 7000 6000 5000 4000 8000 8002 8003 8004 8005 3000 2000 1000 0 7ffe 12 0 00 0 14 850 759 7396 7353 +7*&
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frequency e khz thd, harmonics e db e 60 0 e 65 e 70 e 75 e 80 e 85 e 90 e 95 e 100 e 105 e 110 e 115 10 100 1k 110 105 100 95 90 85 80 75 70 65 60 sfdr e db sfdr thd 2 nd harmonic 3 rd harmonic 115 +7*4+
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8 code dnl e lsb 3 0 16384 65536 32768 49152 0 e 1 e 2 e 3 2 1 +7*$
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* frequency e khz amplitude e db of full scale 0 0 57 228 114 171 e 60 e 80 e 100 e 120 e 20 e 40 e 140 e 160 285 f s = 571ksps f in = 45.01khz snr = 87db thd = e 96db sfdr = 98db sinad = 86.5db +7*2''+7 sampling rate e sps operating current e a 100k 0.001 0.1 10k 1k 100 10 1 0.1 0.01 1 10 100 1k 10k 100k 1m avdd, warp/normal dvdd, warp/normal avdd, impulse dvdd, impulse ovdd, all modes +7*5-
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, code e hexa counts 10000 8002 7ffd 8001 7ffe 8000 7000 6000 5000 4000 9000 8000 8003 8004 8005 8006 3000 2000 1000 0 0 0 79 151 1 0 0 7fff 3336 3303 9514 +7*%
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frequency e khz snr and s/[n+d] e db 100 110 1k 100 85 80 75 70 95 90 enob snr sinad 15.0 14.5 14.0 13.5 13.0 12.5 12.0 enob e bits +7*3,!,9:!;<!-= '
8 50 0 t 12 delay e ns c l e pf 200 50 20 10 0 100 150 30 40 ovdd = 2.7v, 85 c ovdd = 2.7v, 25 c ovdd = 5v, 85 c ovdd = 5v, 25 c +7*6+ ) * * )
ad7650 #(# circuit information the ad7650 is a very fast, low power, single supply, precise 16-bit analog-to-digital converter (adc). the ad7650 features different modes to optimize performances according to the applications. in warp mode, the ad7650 is capable of converting 570,000 samples per second (570 ksps). the ad7650 provides the user with an on-chip track/hold, successive approximation adc that does not exhibit any pipe- line or latency, making it ideal for multiple multiplexed channel applications. the ad7650 can be operated from a single 5 v supply and be interfaced to either 5 v or 3 v digital logic. it is housed in 48-lead lqfp or in a tiny 48-lfcsp packages that save space and allows flexible configurations as either serial or parallel interface. the ad7650 is pin-to-pin compatible with the ad7664. converter operation the ad7650 is a successive-approximation analog-to-digital converter based on a charge redistribution dac. figure 3 shows the simplified schematic of the adc. the capacitive dac con sists of an array of 16 binary weighted capacitors and an additional lsb capacitor. the comparator?s negative input is connected to a dummy capacitor of the same value as the capacitive dac array. during the acquisition phase, the common terminal of the array tied to the comparator?s positive input is connected to agnd via sw a . all independent switches are connected to the analog input in+. thus, the capacitor array is used as a sampling capacitor and acquires the analog signal on in+ input. similarly, the dummy capacitor acquires the analog signal on ine input. when the cnvst input goes low, a conversion phase is initiated. when the conversion phase begins, sw a and sw b are opened first. the capacitor array and the dummy capacitor are then disconnected from the inputs and connected to the refgnd input. therefore, the differential voltage between in+ and ine captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbal- anced. by switching each element of the capacitor array between refgnd or ref, the comparator input varies by binary- weighted voltage steps (v ref /2, v ref /4,...v ref /65536). the control logic toggles these switches, starting with the msb first, to bring the comparator back into a balanced condition. after the completion of this process, the control logic generates the adc output code and brings busy output low. modes of operation the ad7650 features three modes of operations, warp, normal, and impulse. each of these modes is more suitable for specific applications. the warp mode allows the fastest conversion rate up to 570 ksps. however, in this mode, and this mode only, the full specified accuracy is guaranteed only when the time between conversion does not exceed 1 ms. if the time between two consecutive conversions is longer than 1 ms, for instance, after power-up, the first conversion result should be ignored. this mode makes the ad7650 ideal for applications where both high accuracy and fast sample rate are required. the normal mode is the fastest mode (500 ksps) without any limitation about the time between conversions. this mode makes the ad7650 ideal for asynchronous applications such as data acqui- sition systems, where both high accuracy and fast sample rate are required. it is selected when both impulse and warp are low. the impulse mode, the lowest power dissipation mode, allows power saving between conversions. when operating at 100 sps, for example, it typically consumes only 21 w. this feature makes the ad7650 ideal for battery-powered applications. sw a comp sw b in+ ref refgnd lsb msb 32,768c in e 16,384c 4c 2c c c 65,536c control logic switches control busy output code
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#((# ad7650 transfer functions using the ob/ 2c n 000...000 000...001 000...010 111...101 111...110 111...111 adc code e straight binary analog input v ref e 1.5 lsb v ref e 1 lsb 1 lsb 0v 0.5 lsb 1 lsb = v ref /65536 '
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' table i. output codes and ideal input voltages digital output code (hex) analog straight two?s description input binary complement fsr e 1 lsb 2.499962 v ffff 1 7fff 1 fsr e 2 lsb 2.499923 v fffe 7ffe midscale + 1 lsb 1.250038 v 8001 0001 midscale 1.25 v 8000 0000 midscale e 1 lsb 1.249962 v 7fff ffff efsr + 1 lsb 38 v 0001 8001 efsr 0 v 0000 2 8000 2 notes 1 this is also the code for overrange analog input (v in+ e v ine above v ref e v refgnd ). 2 this is also the code for underrange analog input (v in+ below v ine ). notes 1. the adr421 is recommended with c ref = 47 f. 2. the ad8021 is recommended with a compensation capacitor c c = 10pf, type ceramic npo. 3. optional low jitter
. ad7650 2.5v ref note 1 note 2 u1 d note 3 clock c/ p/dsp serial port digital supply (3.3v or 5v) dvdd 100nf + 10 f 100nf + 10 f 100 100nf + 10 f analog supply (5v) + c ref 1 1 f 4.7nf c c 15 analog input (0v to 2.5v) pd reset impulse warp ser/ ob/
busy sdout sclk in e in+ refgnd ref agnd avdd dgnd dvdd ovdd ognd '
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typical connection diagram figure 5 shows a typical connection diagram for the ad7650.
ad7650 #($# the noise generated by the driver amplifier needs to be kept as low as possible to preserve the snr and transition noise performance of the ad7650. the noise coming from the driver is filtered by the ad7650 analog input circuit one-pole low-pass filter made by r1 and c2 or the external filter if any are used. the driver needs to have a thd performance suitable to that of the ad7650. the ad8021 meets these requirements and is usually appropri- ate for almost all applications. the ad8021 needs an external compensation capacitor of 10 pf. this capacitor should have good linearity as an npo ceramic or mica type. the ad8022 could also be used where dual version is needed and gain of 1 is used. the ad829 is another alternative where high-frequency (above 100 khz) performance is not required. in gain of 1, it requires an 82 pf compensation capacitor. the ad8610 is another option where low bias current is needed in low-frequency applications. voltage reference input the ad7650 uses an external 2.5 v voltage reference. the volt- age reference input ref of the ad7650 has a dynamic input impedance. therefore, it should be driven by a low impedance source with an efficient decoupling between ref and refgnd inputs. this decoupling depends on the choice of the voltage reference, but usually consists of a low esr tantalum capacitor connected to the ref and refgnd inputs with minimum para- sitic inductance. 47 f is an appropriate value for tantalum capacitor when used with one of the recommended reference voltages: the low-noise, low temperature drift adr421 and ad780 voltage references. the low-power adr291 voltage reference. the low-cost ad1582 voltage reference. for applications using multiple ad7650s, it is more effective to buffer the reference voltage with a low-noise, very stable op amp such as the ad8031. care should also be taken with the reference temperature coeffi- cient of the voltage reference which directly affects the full-scale accuracy if this parameter matters. for instance, a 15 ppm/ c tempco of the reference changes the full scale by 1 lsb/ c. note that v ref , as mentioned in the specification table, could be increased to avdd e1.85 v. since the input range is defined in terms of v ref , this would essentially increase the range to make it a 0 v to 3 v input range with a reference voltage of 3 v. the ad780 can be selected with a 3 v reference voltage. power supply the ad7650 uses three sets of power supply pins: an analog 5 v supply avdd, a digital 5 v core supply dvdd, and a digital input/output interface supply ovdd. the ovdd supply allows direct interface with any logic working between 2.7 v and 5.25 v. to reduce the number of supplies needed, the digital core (dvdd) can be supplied through a simple rc filter from the analog supply as shown in figure 5. the ad7650 is independent of power supply sequencing and thus free from supply voltage induced latchup. analog input figure 6 shows an equivalent circuit of the input structure of the ad7650. c2 r1 d1 d2 c1 in+ or in e agnd av d d '
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the two diodes, d1 and d2, provide esd protection for the analog inputs in+ and ine. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 v. this will cause these diodes to become forward-biased and start conducting current. these diodes can handle a forward- biased current of 100 ma maximum. for instance, these conditions could eventually occur when the input buffer?s (u1) supplies are different from avdd. in such case, an input buffer with a short circuit current limitation can be used to protect the part. this analog input structure allows the sampling of the differential signal between in+ and ine. unlike other converters, the ine input is sampled at the same time as the in+ input. by using this differential input, small signals common to both inputs are rejected. for instance, by using ine to sense a remote signal ground, difference of ground potentials between the sensor and the local adc ground are eliminated. during the acquisition phase, the impedance of the analog input in+ can be modeled as a parallel combination of capacitor c1 and the network formed by the series connection of r1 and c2. capacitor c1 is primarily the pin capacitance. the resistor r1 is typically 140 and is a lumped component made up of some serial resistors and the on resistance of the switches. the capacitor c2 is typically 60 pf and is mainly the adc sampling capacitor. during the conversion phase, where the switches are opened, the input impedance is limited to c1. the r1, c2 makes a one- pole low-pass filter that reduces undesirable aliasing effect and limits the noise. when the source impedance of the driving circuit is low, the ad7650 can be driven directly. large source impedances will significantly affect the ac performances, especially the total harmonic distortion. driver amplifier choice although the ad7650 is easy to drive, the driver amplifier needs to meet at least the following requirements: the driver amplifier and the ad7650 analog input circuit must be able together to settle for a full-scale step the capacitor array at a 16-bit level (0.0015%). in the amplifier?s data sheet, the settling at 0.1% to 0.01% is more commonly specified. it could significantly differ from the settling time at 16-bit level and it should therefore be verified prior to the driver selection. the tiny op amp ad8021, which combines ultralow noise and a high-gain bandwidth, meets this settling time requirement even when used with high gain up to 13.
#(%# ad7650 power dissipation vs. throughput operating currents are very low during the acquisition phase, which allows a significant power saving when the conversion rate is reduced as shown in figure 7. this power saving depends on the mode used. in impulse mode, the ad7650 automatically reduces its power consumption at the end of each conversion phase. this feature makes the ad7650 ideal for very low power battery applications. it should be noted that the digital interface remains active even during the acquisition phase. to reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power supply rails (i.e., dvdd or dgnd for all inputs except ext/ int 100k 0.1 power dissipation e w sampling rate e sps 100k 1k 10 1 100 10k 1m 10k 1k 100 10 1 0.1 warp/normal impulse '
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, conversion control figure 8 shows the detailed timing diagrams of the conversion process. the ad7650 is controlled by the signal cnvst cnvst cs rd vrisd busy mode t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 acquire convert acquire convert '
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+ in impulse mode, conversions can be automatically initiated. if cnvst cnvst cnvst t 9 t 8 reset data busy
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6 ,++ although cnvst cnvst cnvst cnvst digital interface the ad7650 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. the serial interface is multiplexed on the parallel data bus. the ad7650 digital interface also accommodates both 3 v or 5 v logic by simply connecting the ovdd supply pin of the ad7650 to the host system interface digital supply. finally, by using the ob/ 2c cs rd cs rd t 1 t 3 t 4 t 11
busy data bus = = 0 t 10 previous conversion data new data '
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ad7650 #(&# previous conversion t 1 t 3 t 12 t 13 t 4 = 0
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< serial interface the ad7650 is configured to use the serial interface when the ser/ par master serial interface internal clock the ad7650 is configured to generate and provide the serial data clock sclk when the ext/ int parallel interface the ad7650 is configured to use the parallel interface when the ser/ par current conversion busy data bus t 12 t 13 '
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sync sclk sdout t 28 t 29 t 14 t 18 t 19 t 20 t 21 t 24 t 26 t 27 t 23 t 22 t 16 t 15 123 141516 d15 d14 d2 d1 d0 x ext/
= 0 rdc/sdin = 0 invsclk = invsync = 0 t 25 t 30 '
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#(2# ad7650 ext/
= 0 rdc/sdin = 1 invsclk = invsync = 0 t 3 t 1 t 17 t 14 t 19 t 20 t 21 t 24 t 26 t 25 t 27 t 23 t 22 t 16 t 15 d15 d14 d2 d1 d0 x 12 3 141516 t 18 busy ,
sync sclk sdout '
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< usually, because the ad7650 is used with a fast throughput, the mode master, read during conversion is the most recommended serial mode when it can be used. in read-during-conversion mode, the serial clock and data toggle at appropriate instants which minimize potential feedthrough between digital activity and the critical conversion decisions. in read-after-conversion mode, it should be noted that, unlike in other modes, the signal busy returns low after the 16 data bits are pulsed out and not at the end of the conversion phase which results in a longer busy width. slave serial interface external clock the ad7650 is configured to accept an externally supplied serial data clock on the sclk pin when the ext/ int cs cs rd external discontinuous clock data read after conversion though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. figure 15 shows the detailed timing diagrams of this method. after a conversion is complete, indicated by busy returning low, the result of this conversion can be read while both cs rd cnvst
ad7650 #(3# sclk sdout d15 d14 d1 d0 d13 x15 x14 x13 x1 x0 y15 y14 busy sdin ext/
= 1 invsclk = 0 t 35 t 36 t 37 t 31 t 32 t 16 t 33 x15 x14 x 1 2 3 14151617 18 = 0 t 34 '
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< sdout sclk d1 d0 x d15 d14 d13 123 141516 t 3 t 35 t 36 t 37 t 31 t 32 t 16
busy ext/
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< sclk sdout rdc/sdin busy busy data out ad7650 #1 (downstream) busy out
sclk ad7650 #2 (upstream) rdc/sdin sdout sclk in in
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external clock data read during conversion figure 16 shows the detailed timing diagrams of this method. during a conversion, while both cs rd
#(4# ad7650 microprocessor interfacing the ad7650 is ideally suited for traditional dc measurement appli- cations supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. the ad7650 is designed to interface either with a parallel 16-bit-wide interface or with a general-purpose serial port or i/o ports on a microcontroller. a variety of external buffers can be used with the ad7650 to prevent digital noise from coupling into the adc. the following sections illustrate the use of the ad7650 with an spi-equipped microcontroller, the adsp-21065l and adsp-218x signal processors. spi interface (mc68hc11) figure 18 shows an interface diagram between the ad7650 and an spi-equipped microcontroller like the mc68hc11. to accom- modate the slower speed of the microcontroller, the ad7650 acts as a slave device and data must be read after conversion. this mode allows also the daisy chain feature. the convert command could be initiated in response to an internal timer interrupt. the reading of output data, one byte at a time, if necessary, could be initiated in response to the end-of-conver sion signal (busy going low) using to an interrupt line of the micro controller. the serial peripheral interface (spi) on the mc68hc11 is configured for master mode (mstr = 1), clock polarity bit (cpol) = 0, clock phase bit (cpha) = 1 and spi interrupt enable (spie = 1) by writing to the spi control reg- ister (spcr). the irq is configured for edge-sensitive-only operation (irqe = 1 in option register). mc68hc11
ad7650 busy miso/sdi sck i/o port sdout sclk invsclk ext/
ser/ dvdd additional pins omitted for clarity ovdd '
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adsp-21065l in master serial interface as shown in figure 19, the ad7650 can be interfaced to the adsp-21065l using the serial interface in master mode without any glue logic required. this mode combines the advantages of reducing the number of wire connections and being able to read the data during or after conversion at user convenience. the ad7650 is configured for the internal clock mode (ext/ int rfs adsp-21065l sharc
ad7650 sync dr rclk flag or tfs sdout sclk invsync invsclk ext/
rdc/sdin ser/ dvdd additional pins omitted for clarity ovdd or ognd '
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ad7650 #(5# application hints bipolar and wider input ranges in some applications, it is desired to use a bipolar or wider ana- log input range like, for instance, 10 v, 5 v or 0 v to 5 v. although the ad7650 has only one unipolar range, by simple modifications of the input driver circuitry, bipolar and wider input ranges can be used without any performance degradation. figure 20 shows a connection diagram which allows that. compo- nents values required and resulting full-scale ranges are shown in table ii. u1 2.5v ref analog input r2 r3 r4 100nf r1 u2 c ref in+ in e ref refgnd 1mf ad7650 5v 10nf '
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table ii. component values and input ranges input range r1 r2 r3 r4 10 v 250 2 k 10 k 8 k 5 v 500 2 k 10 k 6.67 k 0 v to e5 v 1 k 2 k none 0 for applications where accurate gain and offset are desired, they can be calibrated by acquiring a ground and a voltage reference using an analog multiplexer, u2, as shown for bipolar input ranges in figure 20. layout the ad7650 has very good immunity to noise on the power supplies as can be seen in figure 9. however, care should still be taken with regard to grounding layout. the printed circuit board that houses the ad7650 should be designed so the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. digital and analog ground planes should be joined in only one place, preferably underneath the ad7650 or, at least, as close as possible to the ad7650. if the ad7650 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point, which should be established as close as possible to the ad7650. it is recommended to avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the ad7650 to avoid noise coupling. fast switching signals like cnvst n evaluating the ad7650 performance a recommended layout for the ad7650 is outlined in the evaluation board for the ad7650. the evaluation board package includes a fully assembled and tested evaluation board, documen tation, and software for controlling the board from a pc via the eval-control board.
#(6# ad7650 outline dimensions dimensions shown in inches and (mm). 48-lead quad flatpack (lqfp) (st-48) seating plane 0.006 (0.15) 0.002 (0.05) top view (pins down) 1 12 13 25 24 36 37 48 0.019 (0.5) bsc 0.276 (7.00) bsc sq 0.011 (0.27) 0.006 (0.17) 0.354 (9.00) bsc sq 0.063 (1.60) max 0.030 (0.75) 0.018 (0.45) 0.008 (0.2) 0.004 (0.09) 08 min coplanarity 0.003 (0.08) 7 0 0.057 (1.45) 0.053 (1.35) controlling dimensions are in millimeters; inch dimensions are rounded-off millimeter equivalents for reference only and are not appropriate for use in design 48-lead frame chip scale flatpack (lfcsp) (cp-48) pin 1 indicator top view 0.266 (6.75) bsc sq 0.276 (7.0) bsc sq 1 48 1 2 13 37 36 24 25 bottom view 0.215 (5.45) 0.209 (5.30) sq 0.203 (5.15) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.020 (0.50) 0.016 (0.40) 0.012 (0.30) 0.012 (0.30) 0.009 (0.23) 0.007 (0.18) 0.020 (0.50) bsc 0.031 (0.80) max 0.026 (0.65) nom 128 max 0.039 (1.00) max 0.033 (0.85) nom 0.008 (0.20) ref 0.002 (0.05) 0.0004 (0.01) 0.0 (0.0) paddle connected to agnd controlling dimensions are in millimeters; inch dimensions are rounded-off millimeter equivalents for reference only and are not appropriate for use in design
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